This relates to integrated circuits and more particularly, to systems for performing simulation and debugging of partial reconfiguration on integrated circuits using a hybrid model.
A programmable integrated circuit (e.g., field programmable gate array) has programmable elements that are loaded with full configuration data. The full configuration data in the programmable elements is used to configure programmable logic on the integrated circuit to store data or perform a custom logic function. Partial reconfiguration (PR) enables a user to define and constrain a PR partition for an integrated circuit during logic design and to reconfigure the PR partition during user mode.
When a PR partition is defined in a user logic design, PR bit streams are generated along with the full configuration data. The generated PR bit streams may then be used to reconfigure the defined PR partition during user mode. Partitions on the integrated circuit that are non-reconfigurable in user mode (also referred collectively as a static partition) are configured during complete device configuration before entering user mode (i.e., before the device enters normal operational mode).
In practice, performing PR operations on an integrated circuit that has been configured based on an erroneous design (e.g., having an erroneously designed PR region) can cause errors to occur in the integrated circuit. Hardware on the integrated circuit is typically used to perform testing and debugging operations to identify and correct such errors. However, performing testing and debugging of PR operations in hardware can require an excessive amount of time and processing resources.